Verilog has two types of assignments within always blocks:.Statements within a fork-join // Module instantiation () statement in an always block // Instantiation of built-in gate primitive execute concurrently gate_type_keyword () endmodule Spring 2007 Lec #8 - HW Synthesis 18. ![]() ![]() Statements between the begin and begin end in an always block execute // Procedural assignments // if statements sequentially from top to bottom // case, casex, and casez statements (however, beware of blocking versus // while, repeat and for loops non-blocking assignment) // user task and user function calls end.Order of these statements is assign = irrelevant, all execute concurrently // always block always.followed by wire, reg, integer, task and function declarations */ /* Describe hardware with one or more continuous assignments, always blocks, module instantiations and gate instantiations */ // Continuous assignment wire Module Template Synthesis tools expects to find modules in this format.
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